๐๏ธ Recruiting Body:
Centre for Development of Advanced Computing (C-DAC), Bangalore
Advt No.: C-DAC/JIT/03/2025 – BLR
Type: Contract-based positions
๐ Important Dates:
Event | Date |
---|---|
Notification Release | 31 May 2025 |
Start Date to Apply Online | 31 May 2025 |
Last Date to Apply Online | 20 June 2025 |
Interview Date | Will be informed via email only |
๐งพ Application Details:
- Mode of Application: Online
- Application Fee: No fee required
- Apply Online: https://careers.cdac.in/advt-search.aspx
- Official Website: https://www.cdac.in
๐ค Eligibility Criteria:
โ Educational Qualifications:
Candidates must possess any of the following degrees in relevant disciplines:
- B.E./B.Tech
- M.E./M.Tech
- M.Sc
- MCA
- M.Phil / Ph.D
Note: Candidates must have qualifications relevant to the post they are applying for. Specific domains like Embedded Systems, VLSI, Quantum Computing, AI, etc., are listed with corresponding posts.
๐ Age Limit:
- Minimum Age: 35 years
- Maximum Age: 56 years
- Age Relaxation: Applicable as per Government of India norms
๐ Post-wise Vacancy Details:
Total Vacancies: 311
Here is the complete breakup of posts:
Post Name | Total Posts |
---|---|
Project Engineer – AI Library and Framework Development | 05 |
Project Engineer – Backend Engineer | 03 |
Project Engineer – Compiler and Parallel Programming Language | 07 |
Project Engineer – Embedded Firmware Development | 08 |
Project Engineer – Embedded Hardware Design Engineer | 08 |
Project Engineer – IT Infrastructure | 02 |
Project Engineer – Mathematics and Computing | 03 |
Project Engineer – Mechatronics/Robotics/Mechanical | 01 |
Project Engineer – MPI, Math Libraries and Communication Libraries | 07 |
Project Engineer – Quantum Computing | 13 |
Project Engineer – VLSI (FPGA/ASIC) | 15 |
Project Manager – Electronics for Photonic Quantum Processors | 01 |
Project Manager – Firmware/BIOS/BMC/Server/PCB Design | 03 |
Project Manager – Networking and Communication | 01 |
Project Manager – Quantum Communication & Photonics | 01 |
Project Manager – VLSI FPGA/ASIC | 01 |
Project Manager – Cyber Security | 01 |
Project Manager – Electronics Hardware Design | 02 |
Project Manager – Embedded Systems & FPGA Design (Quantum) | 01 |
Project Manager – HPC Cluster Management | 01 |
Project Manager – IT Infrastructure | 01 |
Project Manager – QKD Network Deployment | 01 |
Project Manager – Quantum Computing | 01 |
Senior Project Engineer – Photonic Quantum Processors | 01 |
Senior Project Engineer – Software for Quantum Technologies | 01 |
Senior Project Engineer – AI Library and Framework Development | 02 |
Senior Project Engineer – Compiler and Parallel Programming | 03 |
Senior Project Engineer – FPGA & Embedded Systems | 05 |
Senior Project Engineer – Embedded Firmware Development | 04 |
Senior Project Engineer – Embedded Hardware Design | 04 |
Senior Project Engineer – HPC Cluster Administrator | 03 |
Senior Project Engineer – MEP/Electrical (Datacenter) | 01 |
Senior Project Engineer – MPI, Math Libraries | 03 |
Senior Project Engineer – Networking | 02 |
Senior Project Engineer – QKD Network Deployment & R&D | 01 |
Senior Project Engineer – VLSI FPGA/ASIC | 08 |
SPE – Quantum Photonics | 01 |
General Project Engineer | 100 |
Sr. Project Engineer / Project Lead / Module Lead | 70 |
PM / Program Manager / Delivery Manager / Knowledge Partner | 15 |
๐ต Salary Structure (CTC):
Post Level | Salary Range (CTC) |
---|---|
Project Engineer | โน4.49 LPA to โน7.11 LPA |
Senior Project Engineer / Lead / Module Lead | โน8.49 LPA to โน14 LPA |
Project Manager / Program Delivery Manager / Knowledge Partner | โน12.63 LPA to โน22.90 LPA |
Note: Candidates with more experience may be offered a higher salary within the range.
๐ Selection Process:
- Shortlisting based on eligibility and experience
- Interview (only via email communication)
- Further evaluation (if required) may include technical interviews or tests
๐ Important Links:
- ๐ Apply Online: Click Here
- ๐ Download Notification: Click Here
- ๐ Official Website: https://www.cdac.in